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MOS INTEGRATED CIRCUIT
PD16430A
1/2, 1/3, 1/4 DUTY LCD CONTROLLER/DRIVER
The PD16430A is an LCD controller/driver that enables the display of LCDs of 1/2 duty, 1/3 duty and 1/4 duty cycle. The LCD controller contained in the PD16430A employs serial data transfer and uses an automatic increment function for data addresses which eliminates the need to set addresses newly each time. The LCD driver uses a medium voltage output (14 V max.), which enables higher contrast and a wider viewing angle even with a 1/3 or 1/4 duty cycle. By using an on-chip drive bias circuit, it is possible to eliminate the need for external resistors.
FEATURES
* LCD direct drive (medium voltage output: 14 V MAX.) * Choice of 3 duty cycles 1/2 duty, 1/3 duty, 1/4 duty * Display dot number: 1/2 duty: 120 1/3 duty: 160 1/4 duty: 240 * 2 types of drive bias 1/2 bias, 1/3 bias * Choice of 4 types of frame frequency * Multi-chip configuration possible * Control through 8-bit serial interface * On-chip power-on reset circuit * Low-power dissipation CMOS * 3.5 to 6.0 V logic supply voltage
ORDERING INFORMATION
Part number Package 80-pin plastic QFP (14 x 20)
PD16430AGF-3B9
Document No. IC-2776 (1st edition) (O.D. No. IC-8302) Date Published March 1997 N Printed in Japan
(c)
1994
PD16430A
PIN CONFIGURATION (Top View)
VDD LCDOFF BUSY CLK
DATA STB SYNC VSS OSCOUT
80 7978 77 76 7574 73 72 7170 69 68 6766 65 LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 LCD16 LCD17 LCD18 LCD19 LCD20 LCD21 LCD22 LCD23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2627 28 29 3031 32 33 3435 36 37 3839 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 COM1 COM0 LCD59 LCD58 LCD57 LCD56 LCD55 LCD54 LCD53 LCD52 LCD51 LCD50 LCD49 LCD48 LCD47 LCD46 LCD45 LCD44 LCD43 LCD42 LCD41 LCD40 LCD39 LCD38
LCD24 LCD25
Remark Be sure to leave Pin 33 open since it is connected to the lead frame.
2
LCD26 LCD27 LCD28 LCD29 LCD30 LCD31 NC VSS LCD32 LCD33 LCD34 LCD35 LCD36 LCD37
OSCIN VLCD VLC0
VLC1 VLC2 COM3 COM2
PD16430A
PIN FUNCTIONS
No. 1 to 32 35 to 62 Symbol LCD0 to LCD31 LCD32 to LCD59 I/O Output Output Type CMOS Description These pins serve as the LCD driver's segment signal output pins. The following display modes can be selected for the LCD driver. Duty 1/2 Bias 1/2 Display Dot No. 120 Frame frequency (Hz) (fosc = 140 kHz) fosc fosc fosc fosc 256 , 512 , 1024 , 2048 (547) (273) (137) (68) fosc fosc fosc fosc 384 , 768 , 1536 , 3072 (365) (182) (91) (46) fosc fosc fosc fosc 512 , 1024 , 2048 , 4096 (273) (137) (68) (34)
1/3
1/3
160
1/4
1/3
240
A matrix of these segment signal output pins and COM3, COM2, COM1 and COM0 pins enables the maximum display of 240 dots (1/4 duty selected). The output voltage of the segment signal output pins is supplied by the VLCD pin. The output voltage of the segment signal output pin is supplied by dividing and outputting 0 to VLCD voltage using any driving method (any bias method). Either internal or external voltage dividing resistor can be selected. 63 to 66 COM0 to COM3 Output CMOS These pins serve as the LCD driver's common signal output pins. The LCD driver can select three display modes. A matrix of these common signal output pins and LCD59 through LCD0 pins enables the maximum display of 240 dots (1/4 duty selected). The output voltage of the common signal output pins is supplied by the VLCD pin. VDD to 14 V voltage is supplied by this pin. The output voltage of the common signal output pins is supplied by dividing and outputting 0 to VLCD voltage using any driving method (any bias method). Either internal or external dividing resistor can be selected. 67 68 69 70 VLC2 VLC1 VLC0 VLCD -- -- These pins serve as the LCD driver's drive voltage generation pins. The drive voltage can be set by using either these pins or the on-chip drive voltage generation circuit, as specified by command data. This pin supplies the LCD driver's supply voltage. VDD to 14 V voltage is supplied to this pin. The output voltage of the segment signal and command signal output pins is supplied by dividing and outputting the voltage applied to these pins using any driving method (any bias method). Do not supply a voltage exceeding VDD to the VLCD pin before the device's supply voltage reaches 3.5 V, as this may cause incorrect display.
--
--
3
PD16430A
No. 71 72 Symbol OSCIN OSCOUT I/O I/O Output Type CMOS Description These pins serve to connect the resistors of the system clock RC oscillator.
OSCIN 70
OSCOUT 71
100 k When several devices are used, connect as follows: OSCIN 70 100 k
34 73 74 VSS -- -- GND pin for device.
OSCOUT 71
OSCIN 70
OSCOUT 71
SYNC
I/O
Nch Open drain
Synchronous signal I/O pin. This pin is used to synchronize two or more PD16430A's. At this time, each chip must be wire-ORed and a pull-up resistor (5 k to 10 k) is required. This pin must be pulled up even when only one PD16430A is used. Strobe signal input pin for device's select signal and serial communications. This pin serves to latch display RAM data outputs, set the command data receive mode and initialize serial communications. Serial communication is enabled when this signal is a logic low. When this pin is a logic high, shift clocks that are input are ignored. (1) Display RAM data output buffer latch function The internal display RAM data output is latched to the output latch circuit at the rising edge of the STB signal when the BUSY pin outputs a logic high. However, latch timing depends on the LATCH MD and LATCH flags. The latch time is 504.5/fOSC. When the BUSY signal is a logic low, latching can cause incorrect display. (2) Command data receive mode setting The command data receive mode is set by the rising edge of the STB signal when the BUSY pin outputs a logic high. Once the command data receive mode is set, the initial byte (8 bits) is processed as a command. The command data processing time is approximately 300 ns. The BUSY signal does not change during this time. (3) Serial communication is initialized by the rising edge or the falling edge of the STB signal when the BUSY pin outputs a logic low. Once serial communication is initialized, the command data receive mode is started. During command data decoding or display data RAM interrupt, the STB signal interrupts processing and initializes serial communications. At this time, all displays are turned off (LCDON flag is reset).
75
STB
Input
--
76
DATA
Input
--
This pin inputs serial data for serial communication at the rising edge of the shift clock. This pin inputs a shift clock for serial communication. The signal is output at the rising edge of the shift clock signal.
77
CLK
Input
--
4
PD16430A
No. 78 Symbol BUSY I/O Output Output Type Nch Open drain Description This pin outputs the serial communication status and the internal data processing status. When this signal is a logic high, serial communication is executed. When this signal is a logic low, it indicates that the display RAM data is latched to the output buffer. When the power-on reset circuit is operating, this pin holds a logic low until a rising or falling signal is input to the STB pin. This pin serves to turn off all the LCD displays. When a logic low is input to this pin, all LCD displays are turned off. Display RAM data is maintained. Since displays are turned off only by the output driver, serial communications can be executed as usual. To turn on displays, it is necessary to input a logic high to this pin and reset the LCDON flag. This pin is a power supply pin to the device. A voltage of 3.5 to 6.0 V is supplied to this pin. When the supply voltage rises from 0 V to 3 V, or when it reaches a value under 3 V and then rises again, the power-on reset circuit starts operating and the device is set to its initialized state. When the device is in its initialized state, all displays are turned off (segment and common signals are fixed to VLCD). Do not supply a voltage higher than VDD to the VLCD pin before the supply voltage reaches 3.5 V as this will cause incorrect display.
79
LCDOFF
Input
--
80
VDD
--
--
5
PD16430A
BLOCK DIAGRAM
LCD59
COM3
Segment driver (2 x 60 circuits)
Common driver
COM0
LCD0
Level shifter (60 circuits)
Level shifter
Drive voltage generation circuit
VLCD VLCD0 VLCD1 VLCD2
Selector (60 circuits)
Selector
LCDOFF
0123
Output data latch (4 x 60 bits)
0123
Latch pulse generator (60 bits)
RES Timing controller
RES
0
1
2
3
Data selector OSCIN Oscillator OSCOUT
Read address counter Write address counter
29
Display memory RAM
29
RES RES Power-on detector VDD
8 x 30 bits
0
Write controller
0
RES
BUSY
Command register VSS
STB
Command decoder
DATA CLK
8 bit shift register
6
PD16430A
Display RAM Addresses and Display Dots Display RAM temporarily stores display data that has been sent serially. Display RAM addresses are allocated in units of 8 bits (group address), and it is possible to store the display data of a group address transferred at one time. The relations between group addresses and display dots for the three display modes are shown below. (1) 1/2 duty
COM1 1 3 5 7 COM2 0 2 4 6 Group address 0 1 2 3 4 9 10 11 12 13 14
(2) 1/3 duty
COM2 2 5 7 COM1 1 4 6 COM0 0 3 Group address 0 1 2 3 4 5 12 13 14 15 16 17 18 19
The shaded parts are always 1.
(3) 1/4 duty
COM3 3 7 COM2 2 6 COM1 1 5 COM0 0 4 Group address 0 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29
Remark During auto incrementing, incrementing past the last group address of each duty (for example group address 14 in the case of 1/2 duty) brings the counter back to "0."
LCD 55 LCD 56 LCD 57 LCD 58 LCD 59
LCD 0 LCD 1 LCD 2 LCD 3 LCD 4 LCD 5 LCD 6 LCD 7 LCD 8 LCD 9
LCD 55 LCD 56 LCD 57 LCD 58 LCD 59
LCD 0 LCD 1 LCD 2 LCD 3 LCD 4 LCD 5 LCD 6 LCD 7 LCD 8 LCD 9
LCD 55 LCD 56 LCD 57 LCD 58 LCD 59
LCD 0 LCD 1 LCD 2 LCD 3 LCD 4 LCD 5 LCD 6 LCD 7 LCD 8 LCD 9
7
PD16430A
Commands Commands serve to set the LCD driver's display mode and status. The first byte (8 bits) after the falling edge input of the STB signal is processed as a command. The various types of commands are shown below. (1) Display Mode Setting Command
MSB F R C K 1 F R C K 0 L C D M D 1 LSB L C D M D 0
0
0
--
--
Display mode setting flag 00 : 1/2 duty, 1/2 bias 01 : 1/2 duty, 1/2 bias 10 : 1/3 duty, 1/3 bias 11 : 1/4 duty, 1/3 bias
Frame frequency setting flag 00 : (fOSC/128) x n, n = duty (1/2, 1/3, 1/4) 01 : (fOSC/256) x n 10 : (fOSC/512) x n 11 : (fOSC/1024) x n
Don't Care
Values at power-on reset --------
--
--
8
PD16430A
(2) Data Setting Command
MSB L A T C H M D A D D R I N C R / W M D 1 LSB R / W M D 0
0
1
--
--
Sets data write mode 00 : WRITE 01 : WRITE 10 : Setting prohibited 11 : Setting prohibited
Sets data address increment mode. 0 : Auto increment (increments group address after input/output of 8 bits of data) 1 : Holds address even after data input/output.
Sets data latch mode. 0 : Depends on latch flag of status setting command. 1 : Latches to output buffer at the rising edge of the STB signal immediately after data input.
Don't Care
Values at power-on reset -- -- 0 0 0 0
9
PD16430A
(3) Status setting command
MSB T E S T 1 T E S T 0 L C D E X A D D R R E S L A T C H LSB L C D O N
1
0
Turns on all displays. (no display unless logic high is input to LCDOFF pin) 0 : All displays are turned off at the rising edge of the STB signal immediately after this command is input. 1 : All displays are turned on at the rising edge of the STB signal immediately after this command is input.
Sets method for latching to RAM data output bufferNote 0 : Does not latch RAM data to output buffer. 1 : Latches to output buffer at every rising edge of STB signal.
Resets group address. 0 : Does not reset group address. 1 : Resets group address at rising edge of STB signal following data write (000000B).
Sets drive voltage supply method. 0 : External 1 : Internal
Sets test mode. 00 : Normal operation (master) 01 : Normal operation (slave) 10 : Test mode 11 : Test mode
Values at power-on reset 0 0 0 0 0 0
Remark LATCH MD flag and LATCH flag The relations between the LATCH MD flag and the LATCH flag are shown below.
Mode 1 2 3 4 LATCH MD 0 0 1 1 LATCH 0 1 0 1 Operation Does not latch RAM data to output buffer. Latches every time to output buffer at rising edge of STB signal. Latches to output buffer at rising edge of STB signal immediately after data input. Latches every time to output buffer at rising edge of STB signal.
In modes 2 and 4, since latching to the output buffer is executed at the rising edge of the STB signal when only a command has been issued from the STB pin, busy status comes at each rising edge of the STB signal.
10
PD16430A
(4) Address setting command
MSB LSB
1
1
0
b4
b3 b2
b1 b0
Sets RAM group address. 000000 to 001110 (1/2 duty) 000000 to 010011 (1/3 duty) 000000 to 011101 (1/4 duty)
Values at power-on reset -- 0 0 0 0 0
11
12
DATA CLK Command Command Data STB BUSY <1> <2> <3> <4> <5> <6> <4> <7> <4> Data Command 504.5/fOSC <8> <4> <5> <9> <4> <10>
Data transmission format
<1> Start serial communications by setting STB signal to logic low <2> Internal processing time = 300 ns <3> Transmit mode setting command if initialized (duty cycle and others) <4> Internal processing time = 300 ns <5> Wait for command data input after input of STB signal <6> Input data write method or address setting command <7> Transmit (receive) RAM data specified by set address <8> Transmit (receive) RAM data specified by set address <9> Input data write method or address setting command <10> Execute RAM data latch or display enable by rising STB pin. <11> Output logic low from BUSY pin during data latching. The time is 504.5/fOSC.
PD16430A
2) Functions of power-on reset
1) Device operation
Power-on reset
(2) Initializes serial communication.
(1) Turns off all displays.
VDD
Power-on reset voltage (3 V)
Internal POC
OSC1 BUSY
STB <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
<1> Apply supply voltage VDD. <2> When VDD becomes higher than power-on reset voltage, device starts operating. <3> Device stabilization time (less than 10 ms for internal oscillator) During this time, do not execute STB pin input. <4> After oscillation stabilization time is over, an STB signal input is waited for. <5> When a logic high or logic low STB signal is input, a logic high is output from the BUSY pin, and a command input is waited for. <6> A command input is waited for. <7> When VDD becomes again a value lower than the power-on reset voltage, device operation stops. <8> When VDD becomes again a value higher than the power-on reset voltage, device operation starts. <9> Oscillation stabilization time (less than 10 ms for internal oscillator). <10> After oscillation stabilization time is over, an STB signal input is waited for. <11> When a logic high or logic low STB signal is input, a logic high is output from the BUSY pin, and a command input is waited for.
PD16430A
13
<12> A command input is waited for.
PD16430A
Application Data transmission examples according to address increment mode
DATA
Command 1
Command 2
Command 3
Data 1
Data n-1
Data n
CLK STB
Command 1 0 0 - - 0 0 1 0 1/3 duty, 1/3 bias Frame frequency: (fOSC/128) x (1/3) Don't Care Command 2 0 1 - - 1 0 0 0 Data write mode Data address increment mode Latches to output buffer at rising edge of STB signal immediately after data input Don't Care Command 3 1 0 0 0 1 1 0 1 Display on Doesn't latch RAM data to output buffer Resets RAM group address Internal drive voltage Normal operation Data 1 to n b7 b6 b5 b4 b3 b2 b1 b0 Display data (When VDD is applied, data address is initialized to 000000B Because the address increment mode is selected, the address is incremented every time 8 bits of data are input, and the next data input is waited for.)
14
PD16430A
Absolute Maximum Ratings (Ta = 25 C, GND = 0 V)
Parameter Logic supply voltage Logic input voltage Logic output voltage Driver supply voltage Driver input voltage Driver output voltage Operating temperature range Storage temperature range Permissible package power dissipation Symbol VDD VI1 VO1 VLCD VLC0 - VLC2 VO2 Topt Tstg Pd Condition Rating -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to +16 -0.3 to VLCD + 0.3 -0.3 to VLCD + 0.3 -40 to +85 -65 to +150 1000 Unit V V V V V V C C mW
Recommended Operating Conditions (Ta = -40 to +85 C, GND = 0 V)
Parameter Logic supply voltage Driver supply voltage Driver input voltage Symbol VDD VLCD VLC0 - VLC2 Condition MIN. 3.5 VDD 0 TYP. MAX. 6.0 14 VLCD Unit V V V
Electrical Characteristics (Ta = -40 to +85 C, VDD = 5 V 10 %, VLCD = 9 to 12 V)
Parameter Input voltage, high Input voltage, low Output voltage, high Symbol VIH VIL VOH OSCOUT, SYNC, BUSY IOH = -1 mA OSCOUT, SYNC, BUSY IOL = 1 mA VIN = VDD VIN = 0 V SYNC, BUSY VO = VDD SYNC, BUSY VO = 0 V COM0 - COM3, VLCD = 9 V llol = 100 A LCD0 - LCD59, VLCD = 9 V llol = 100 A fOSC = 140 kHz VLCD = 12 V, without load -10 -10 10 Condition MIN. 0.7*VDD 0 0.9*VDD TYP. MAX. VDD 0.3*VDD Unit V V V
Output voltage, low
VOL
0.1*VDD
V
Input leak current, high Input leak current, low Output leak current, high
IIH IIL ILOH
10
A A A A
Output leak current, low
ILOL
Common output ON resistance
RCOM
1.2
2.4
k
Segment output ON resistance
RSEG
2.0
4.0
k
Logic current dissipation Driver current dissipation
IDD ILCD
100 500
500 1000
A A
15
PD16430A
Switching Characteristics (Ta = -40 to +85 C, VDD = 5 V 10 %, VLCD = 9 to 12 V, RL = 5 k, CL = 150 pF)
Parameter Oscillation frequency BUSY delay time SYNC delay time Symbol fSOC tDBSY tDSYNC R = 100 k STB BUSY Condition MIN. 98 TYP. 140 MAX. 182 1.5 1.5 Unit kHz
s s
Timing Requirements (Ta = -40 to +85 C, VDD = 5 V 10 %, VLCD = 9 to 12 V, RL = 5 k, CL = 150 pF)
Parameter Clock frequency High-level clock pulse width Low-level clock pulse width Shift clock cycle High-level shift clock pulse width Low-level shift clock pulse width Data setup time Data hold time STB removal time STB hold time High-level STB pulse width Low-level STB pulse width SYNC removal time Symbol fc tWHC tWLC tCYK tWHK tWLK tDS tDH tRSTBK tHKSTB tWHSTB tWLSTB tSREM STB CLK From the 8th CLK pulse Condition OSCIN external clock OSCIN external clock OSCIN external clock CLK CLK CLK MIN. 50 3 3 900 400 400 100 200 300 1 1 8.2 250 TYP. MAX. 150 16 16 Unit kHz
s s
ns ns ns ns ns ns
s s s
ns
Output Load Circuit
VDD
5 k
OUTPUT
150 pF
16
PD16430A
Switching Characteristic Waveform Measurement points: Input: 0.7 VDD, 0.3 VDD Output: 0.8 VDD, 0.2 VDD
1/fc tWHC
OSCIN
tWLC tWLSTB tWHSTB
STB
tRSTBK
tHKSTB
tCYK tWLK tWHK
CLK
tDS
tDH
DATA
SYNC timing (master) 1 frame fOSC tDSYNC SYNC 1 frame 1 frame
SYNC timing (slave) 1 frame
tSREM
Internal reset
17
PD16430A
STB
tDBSY
BUSY
18
PD16430A
Application Circuit Example
LCD panel 5 V for driver LCD, COM
LCDOFF BUSY LCD controller/driver DATA CLK STB Power detection OSCOUT SYNC VDD VDD VLCD OSCIN Multi-chip configuration OSCIN SYNC
Microcontroller
5V Battery
5V ACC POWER
Remark Use low-VF diodes such as Schottky-barrier diodes, and make sure that VDD, VLCD, VI, etc. do not exceed absolute maximum ratings of the diodes.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
19
PD16430A
1. PD16430A External Bias Resistor Setting Method
VDD up to 14 V VDD up to 14 V
VLCD R VLC0
VLCD R VLC0 R
PD16430A
VLC1
PD16430A
VLC1
R
R VLC2 LCDOFF VR LCDOFF VR VLC2
EN (H = display on)
EN (H = display on)
VR =
1/2 bias 2 (VLCD - VLC) VLC
VR =
1/3 bias 3 (VLCD - VLC) VLC
VLC is the peak value of the optimum drive voltage for LCD. (it varies depending on the LCD.) R is a resistance of 1 k to 10 k. Select the resistance value according to the load. A larger value for R reduces the power dissipation, but causes drive waveform distortions. Select a largish value for a variable resistor so as to satisfy the equation above. 2. When using internal bias A heavy LCD load may cause distortions in the common waveform. In this case, insert a capacitor for VLC0, VLC1 and VLC2.
VDD up to 14 V
VLCD VLC2 PD16430A VLC1 VLC0
C = 0.001 to 0.1 F
20
PD16430A
Characteristic Curves
fOSC - R Characteristics VDD = +5 V Ta = +25 C 200 k Oscillation frequency fOSC (Hz) Oscillation frequency fOSC (Hz) fOSC - VDD, Ta Characteristics R = 100 k VDD = 5.5 V 100 k VDD = 4.5 V VDD = 3.5 V VDD = 5.0 V
100 k
10 k
0
100 k
200 k 300 k 400 k External resistor R ()
500 k
-40
25 85 Temperature Ta (C)
Recommended Soldering Conditions When soldering on this product, please observe the recommended conditions indicated in the table below. If planning to solder under different conditions, please consult an NEC sales representative.
PD16430AGF-3B9
Soldering method Infrared ray reflow Soldering conditions Peak package temperature: 235 C, time: 30 seconds max. (210 C min.), number of reflow processes: 2, exposure limit: none Note Peak package temperature: 215 C, time: 40 seconds max. (200 C min.), number of reflow processes: 2, exposure limit: none Note Solder temperature: 260 C max., time: 10 seconds max. number of reflow processes: 1, exposure limit: none Note Pin temperature: 300 C max., time: 10 seconds max., exposure limit: none
Note
Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
Note Exposure limit before soldering after dry-package is opened. Storage conditions: 25 C, relative humidity of 65 % or less. Caution Do not apply two or more soldering methods (except partial heating) in combination.
21
PD16430A
80 PIN PLASTIC QFP (14 20)
A B
64 65
41 40
detail of lead end
CD
S Q R
80 1
25 24
F G H P I
M
J
K M N L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.20.2 20.00.2 14.00.2 17.20.2 1.0 1.8 0.350.10 0.15 0.8 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.1250.075 55 3.0 MAX. INCHES 0.913 +0.009 -0.008 0.787 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.008 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0050.003 55 0.119 MAX. S80GF-80-3B9-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
22
PD16430A
[MEMO]
23
PD16430A
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
2

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